This lab describes the process of generating a Versal® ACAP QDMA design containing 4 PFs, 252 VFs and AXI4 Memory Mapped interface connected to the network on chip (NoC) IP and DDR memory. This design has the following configurations:
- AXI4 memory mapped (AXI MM) connected to DDR through the NoC IP
- Gen3 x 16
- 4 physical functions (PFs) and 252 virtual functions (VFs) with Mailbox connections.
- MSI-X interrupts
This lab targets a xcvc1902-vsvd1760-1LP-e-S-es1 part on a VCK5000 board. This lab connects to DDR memory found outside the ACAP.
Lab 2 initial configurations are the same as in Lab 1.So follow "Start the Vivado Design Suite", "Instantiate CIPS IP and "Set the PCIe Reset Pin" section from Lab 1. Refer to Lab1: QDMA AXI MM Interface to NoC and DDR.