Management Mode - 3.3 English

Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2022-11-02
Version
3.3 English

The management mode method for HSDP-over-PCIe imposes more design requirements on the target device and requires more setup, but its throughput is faster and allows for debug of hardened debug cores. Management mode for HSDP-over-PCIe uses the HSDP DMA block to transfer DTPs to DPC and coordinates responses to the Host PC. The HSDP DMA block must be accessible for setup from a PCIe BAR through CPM’s AXI Master Bridge at base address 0xFE5F0000. The physical address is fixed and cannot be remapped in the FPGA address space, as the HSDP DMA is only accessible from an interconnect switch between the CPM interconnect and the NOC. This means that NOC NMU address remapping cannot be employed, and the PCIe BAR must be large enough to reach the HSDP DMA or the master bridge itself must perform address translation.

Figure 1. CIPS IP PS PMC Configuration for Management Mode Debug Using DPC

To enable management mode debug for Versal ACAP that has CPM4, CPM must have at least one AXI BAR enabled and the slave bridge must also be enabled for the DMA transfers to target and to set up address translation to host memory. The PMC master must have the debug hub slave mapped to its address space and the CPM master must have the CPM slave mapped to its address space. For CPM4, you can configure up to 6 AXI BARs, each with address translation, which allows for only 6 apertures. The address translation registers are programmed from the slave bridge interface by the Host PC through the master bridge.

Figure 2. Block Diagram for HSDP-over-PCIe Management Mode Debug for CPM4
Figure 3. Address Map for HSDP-over-PCIe Management Mode Debug for CPM4
Figure 4. AXI BARs for HSDP-over-PCIe Management Mode Debug for CPM4
Figure 5. PCIe BARs for HSDP-over-PCIe Debug for CPM4/CPM5

To enable mgmt mode debug for a Versal ACAP that has CPM5 within it, CPM must have at least one AXI BAR enabled and the slave bridge must also be enabled for the DMA transfers to target. The PMC master must have the debug slave mapped into its address space and the CPM master must have the CPM registers mapped into its address space. The address translation between CPM4 and CPM5 differ significantly. For CPM5, the concept of the BDF table was introduced, which allows for significantly more granularity for address translation within each AXI BAR, even with fewer AXI BARs. The BDF table registers are located in the CPM register space, which are only accessible through the PMC interface by the Host PC from the master bridge.

Figure 6. Block Diagram for HSDP-over-PCIe Management Mode Debug for CPM5