Opening the Example Design and Generating a Bitstream - 3.3 English

Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2022-11-02
Version
3.3 English

A set of example designs are hosted on GitHub in the XilinxCEDStore repository and displayed through Vivado, which can be refreshed with a valid internet connection, including the HSDP-over-PCIe example design. You can also download or clone the GitHub repository to your local machine and point to the that location on your PC. To open the example design, perform the following options:

  1. Launch Vivado.
  2. Navigate to the set of example designs for selection
    • From the Quick Start menu, select Open Example Project, or
    • Select File > Project > Open Example.
  3. From the Select Project Template window, select Versal CPM PCIe Debug and navigate through the menus to select a project location and board part.
  4. In the Flow Navigator, click Generate Device Image to run synthesis, implementation, and generate a programmable device image (.pdi) file that can be loaded to the target FPGA and a probes (.ltx) file used to specify debug information.
Note: You can download or clone the GitHub repository to a local machine from https://github.com/Xilinx/XilinxCEDStore and set the following parameter so that local example designs are displayed in the Select Project template window.
set_param CED.repoPaths <parent-path>/XilinxCEDStore/<optional-path-to-subset-of-designs>