A set of example designs are hosted on GitHub in the XilinxCEDStore repository and displayed through Vivado, which can be refreshed with a valid internet connection, including the HSDP-over-PCIe example design. You can also download or clone the GitHub repository to your local machine and point to the that location on your PC. To open the example design, perform the following options:
- Launch Vivado.
- Navigate to the set of example designs for selection
- From the Quick Start menu, select Open Example Project, or
- Select .
- From the Select Project Template window, select Versal CPM PCIe Debug and navigate through the menus to select a project location and board part.
- In the Flow Navigator, click Generate Device Image to run synthesis, implementation, and generate a programmable device image (.pdi) file that can be loaded to the target FPGA and a probes (.ltx) file used to specify debug information.
set_param CED.repoPaths <parent-path>/XilinxCEDStore/<optional-path-to-subset-of-designs>