PCIe Error Handling - 3.3 English

Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2022-11-02
Version
3.3 English

RP_ERROR_FIFO (RP only)

Error handling is as follows:

  1. Read register 0xE10 (INT_DEC) and check if bits is set to one of: [9] (correctable), [10] (non_fatal) or [11] (fatal).
  2. Read register 0xE20 (RP_CSR) and check if bit [16] is set to see if efifo_not_empty is set.
  3. If FIFO is not empty read FIFO by reading 0xE2C (RP_FIFO_READ)
    1. Error message indicates where the error comes from (i.e, requestor ID) and Error type.

  4. To clear the error, write to 0xE2C (RP_FIFO_READ). Value does not matter

  5. Repeat steps 2 and 3 until 0xE2C (RP_FIFO_READ) bit [18] valid bit is cleared.

  6. Write 1 to register 0xE10 (INT_DEC) to clear bits [9] (correctable), [10] (non_fatal) or [11] (fatal).

RP_PME_FIFO (RP only)

Error handling is a follows:

  1. Read register 0xE10 (INT_DEC) and check if bits [17] is set, which indicates PM_PME message has been received.
  2. Read register 0xE20 (RP_CSR) and check if bit [18] is set to see if pfifo_not_empty is set.

  3. If FIFO is not empty, read FIFO by reading 0xE30 (RP_PFIFO).

    1. Message will indicate where the message comes from (i.e., requestor ID).

  4. To clear the error, write to 0xE30 (RP_PFIFO). Value does not matter.

  5. Repeat steps 2 and 3 until 0xE30 (RP_PFIFO) bit [31] valid bit is cleared.

  6. Write 1 to register 0xE10 (INT_DEC) to clear bits [17].