PCIe to AXI BARs - 3.3 English

Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2022-11-02
Version
3.3 English

For each physical function, the PCIe configuration space consists of a set of five 32-bit memory BARs and one 32-bit Expansion ROM BAR. When SR-IOV is enabled, an additional five 32-bit BARs are enabled for each Virtual Function. These BARs provide address translation to the AXI4 memory mapped space capability, interface routing, and AXI4 request attribute configuration. Any pairs of BARs can be configured as a single 64-bit BAR. Each BAR can be configured to route its requests to the QDMA register space, or the AXI MM bridge master interface.

Request Memory Type

The memory type can be set for each PCIe BAR through GUI configuration.

  • AxCache[0] is set to 1 for modifiable, and 0 for non-modifiable. Selecting the AxCache box sets AxCache[0] to 1.