Poll Mode - 3.3 English

Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2022-11-02
Version
3.3 English

Each engine is capable of writing back completed descriptor counts to host memory. This allows the driver to poll host memory to determine when the DMA is complete instead of waiting for an interrupt.

For a given DMA engine, the completed descriptor count writeback occurs when the DMA completes a transfer for a descriptor, and ie_descriptor_completed and Pollmode_wb_enable are set. The completed descriptor count reported is the total number of completed descriptors since the DMA was initiated (not just those descriptors with the Completed flag set). The writeback address is defined by the Pollmode_hi_wb_addr and Pollmode_lo_wb_addr registers.

Table 1. Completed Descriptor Count Writeback Format
Offset Fields
0x0 Sts_err 7’h0 Compl_descriptor_count[23:0]
Table 2. Completed Descriptor Count Writeback Fields
Field Description
Sts_err The bitwise OR of any error status bits in the channel Status register.
Compl_descriptor_count[23:0] The lower 24 bits of the Complete Descriptor Count register.