QDMA AXI MM Interface to NoC and DDR Lab - 3.3 English

Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2022-11-02
Version
3.3 English

This lab describes the process of generating a VersalĀ® ACAP QDMA design with AXI4 Memory Mapped interface connected to network on chip (NoC) IP and DDR memory. This design has the following configurations:

  • AXI4 memory mapped (AXI MM) connected to DDR through the NoC IP
  • Gen3 x 16
  • 4 physical functions (PFs) and 252 virtual functions (VFs)
  • MSI-X interrupts
This lab provides step by step instructions to configure a Control, Interfaces and Processing System (CIPS) QDMA design and network on chip (NoC) IP. The following figure shows the AXI4 Memory Mapped (AXI-MM) interface to DDR using the NoC IP. At the end of this lab, you can synthesize and implement the design, and generate a Programmable Device Image (PDI) file. The PDI file is used to program the Versal ACAP and run data traffic on a system. For the AXI-MM interface host to chip (H2C) transfers, data is read from Host and sent to DDR memory. For chip to host (C2H) transfers, data is read from DDR memory and written to host.

This lab targets xcvp1202-vsva2785-2MP-e-S-es1 part. This lab connects to DDR memory found outside the Versal ACAP. A constraints file is provided and added to the design during the lab. The constraints file lists all DDR pins and their placement. You can modify the constraint file based on your requirements and DDR part selection.

Figure 1. AXI4 Memory Mapped to DDR Design