This lab describes the process of generating a Versal® ACAP QDMA design with AXI4 Memory Mapped interface connected to network on chip (NoC) IP and DDR memory. This design has the following configurations:
- AXI4 memory mapped (AXI MM) connected to DDR through the NoC IP
- Gen3 x 16
- 4 physical functions (PFs) and 252 virtual functions (VFs)
- MSI-X interrupts
This lab targets xcvp1202-vsva2785-2MP-e-S-es1 part. This lab connects to DDR memory found outside the Versal ACAP. A constraints file is provided and added to the design during the lab. The constraints file lists all DDR pins and their placement. You can modify the constraint file based on your requirements and DDR part selection.