QDMA Descriptor Bypass Input Ports - 3.3 English

Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2022-11-02
Version
3.3 English
Table 1. QDMA H2C-Streaming Bypass Input Port Descriptions
Port Name I/O Description
dma<n>_h2c_byp_in_st_addr [63:0] I 64-bit starting address of the DMA transfer.
dma<n>_h2c_byp_in_st_len [15:0] I The number of bytes to transfer.
dma<n>_h2c_byp_in_st_sop I Indicates start of packet. Set for the first descriptor. Reset for the rest of the descriptors.
dma<n>_h2c_byp_in_st_eop I Indicates end of packet. Set for the last descriptor. Reset for the rest of the descriptors
dma<n>_h2c_byp_in_st_sdi I H2C Bypass In Status Descriptor/Interrupt

If set, it is treated as an indication from the user application to the QDMA to send the status descriptor to host, and to generate an interrupt to host when the QDMA has fetched the last byte of the data associated with this descriptor. The QDMA honors the request to generate an interrupt only if interrupts have been enabled in the H2C SW context for this QID and armed by the driver. This can only be set for an EOP descriptor.

QDMA will hang if the last descriptor without h2c_byp_in_st_sdi has an error. This results in a missing writeback and hw_ctxt.dsc_pend bit that are asserted indefinitely. The workaround is to send a zero length descriptor to trigger the Completion (CMPT) Status.

dma<n>_h2c_byp_in_st_mrkr_req I H2C Bypass In Marker Request

When set, the descriptor passes through the H2C Engine pipeline and once completed, produces a marker response on the interface. This can only be set for an EOP descriptor.

dma<n>_h2c_byp_in_st_no_dma I H2C Bypass In No DMA

When sending in a descriptor through this interface with this signal asserted, it informs the QDMA to not send any PCIe requests for this descriptor. Because no PCIe request is sent out, no corresponding DMA data is issued on the H2C Streaming output interface.

This is typically used in conjunction with dma<n>_h2c_byp_in_st_sdi to cause Status Descriptor/Interrupt when the user logic is out of the actual descriptors and still wants to drive the dma<n>_h2c_byp_in_st_sdi signal.

If dma<n>_h2c_byp_in_st_mrkr_req and h2c_byp_in_st_sdi are reset when sending in a no-DMA descriptor, the descriptor is treated as a NOP and is completely consumed inside the QDMA without any interface activity.

If dma<n>_h2c_byp_in_st_no_dma is set, then both dma<n>_h2c_byp_in_st_sop and dma<n>_h2c_byp_in_st_eop must be set.

If dma<n>_h2c_byp_in_st_no_dma is set, the QDMA ignores the address and length fields of this interface.

dma<n>_h2c_byp_in_st_qid [10:0] I The QID associated with the H2C descriptor ring.
dma<n>_h2c_byp_in_st_error I This bit can be set to indicate an error for the queue. The descriptor will not be processed. Context will be updated to reflect an error in the queue
dma<n>_h2c_byp_in_st_func [11:0] I PCIe function ID
dma<n>_h2c_byp_in_st_cidx [15:0] I The CIDX that will be used for the status descriptor update and/or interrupt (aggregation mode). Generally the CIDX should be left unchanged from when it was received from the descriptor bypass output interface.
dma<n>_h2c_byp_in_st_port_id [2:0] I QDMA port ID
dma<n>_h2c_byp_in_st_valid I Valid. High indicates descriptor is valid, one pulse for one descriptor.
dma<n>_h2c_byp_in_st_ready O Ready to take in descriptor
Table 2. QDMA H2C-MM Channel 0 Descriptor Bypass Input Port Descriptions
Port Name I/O Description
dma<n>_h2c_byp_in_mm_<y>_radr[63:0] I The read address for the DMA data.
dma<n>_h2c_byp_in_mm_<y>_wadr[63:0] I The write address for the dma data.
dma<n>_h2c_byp_in_mm_<y>_no_dma I

H2C Bypass In No DMA

When sending in a descriptor through this interface with this signal asserted, this signal informs the QDMA to not send any PCIe requests for this descriptor. Because no PCIe request is sent out, no corresponding DMA data is issued on the H2C MM output interface.

This is typically used in conjunction with h2c_byp_in_mm_sdi to cause Status Descriptor/Interrupt when the user logic is out of the actual descriptors and still wants to drive the h2c_byp_in_mm_sdi signal.

If h2c_byp_in_mm_mrkr_req and h2c_byp_in_mm_sdi are reset when sending in a no-DMA descriptor, the descriptor is treated as a No Operation (NOP) and is completely consumed inside the QDMA without any interface activity.

If h2c_byp_in_mm_no_dma is set, the QDMA ignores the address. The length field should be set to 0.

dma<n>_h2c_byp_in_mm_<y>_len[27:0] I The DMA data length.

The upper 12 bits must be tied to 0. Thus only the lower 16 bits of this field can be used for specifying the length.

dma<n>_h2c_byp_in_mm_<y>_sdi I

H2C-MM Bypass In Status Descriptor/Interrupt

If set, it is treated as an indication from the User to QDMA to send the status descriptor to host and generate an interrupt to host when the QDMA has fetched the last byte of the data associated with this descriptor. The QDMA will honor the request to generate an interrupt only if interrupts have been enabled in the H2C ring context for this QID and armed by the driver.

QDMA will hang if the last descriptor without h2c_byp_in_mm_sdi has an error. This results in a missing writeback and hw_ctxt.dsc_pend bit that are asserted indefinitely. The workaround is to send a zero length descriptor to trigger the Completion (CMPT) Status.

dma<n>_h2c_byp_in_mm_<y>_mrkr_req I

H2C-MM Bypass In Marker Request

Indication from the User that the QDMA must send a completion status to the User once the QDMA has completed the data transfer of this descriptor.

dma<n>_h2c_byp_in_mm_<y>_qid [10:0] I The QID associated with the H2C descriptor ring.
dma<n>_h2c_byp_in_mm_<y>_error I This bit can be set to indicate an error for the queue. The descriptor will not be processed. Context will be updated to reflect and error in the queue.
dma<n>_h2c_byp_in_mm_<y>_func [11:0] I PCIe function ID
dma<n>_h2c_byp_in_mm_<y>_cidx [15:0] I The CIDX that will be used for the status descriptor update and/or interrupt (aggregation mode). Generally the CIDX should be left unchanged from when it was received from the descriptor bypass output interface.
dma<n>_h2c_byp_in_mm_<y>_port_id [2:0] I QDMA port ID
dma<n>_h2c_byp_in_mm_<y>_valid I Valid. High indicates descriptor is valid, one pulse for one descriptor.
dma<n>_h2c_byp_in_mm_<y>_ready O Ready to take in descriptor
  1. variable <n> : represents different QDMAs (QDMA0 or QDMA1).
  2. variable <y> : represents different Channels, (Channel 0 or Channel 1 ).
Table 3. QDMA C2H-Streaming Bypass Input Port Descriptions 1
Port Name I/O Description
dma<n>_c2h_byp_in_st_csh_addr [63:0] I 64 bit address where DMA writes data.
dma<n>_c2h_byp_in_st_csh_qid [10:0] I The QID associated with the C2H descriptor ring.
dma<n>_c2h_byp_in_st_csh_error I This bit can be set to indicate an error for the queue. The descriptor will not be processed. Context will be updated to reflect and error in the queue.
dma<n>_c2h_byp_in_st_csh_func [11:0] I PCIe function ID
dma<n>_c2h_byp_in_st_csh_port_id[2:0] I QDMA port ID
dma<n>_c2h_byp_in_st_csh_pfch_tag[6:0] I Prefetch tag. The prefetch tag points to the cam that stores the active queues in the prefetch engine. In Cache Bypass mode, you must loop back dma<n>_c2h_byp_out_pfch_tag[6:0]to dma<n>_c2h_byp_in_st_csh_pfch_tag[6:0].In Simple bypass mode, used to pass in the Prefetch tag value from MDMA_C2H_PFCH_BYP_TAG (0x140C) register.
dma<n>_c2h_byp_in_st_csh_valid I Valid. High indicates descriptor is valid, one pulse for one descriptor.
dma<n>_c2h_byp_in_st_csh_ready O Ready to take in descriptor.
  1. AXI-Stream C2H Simple Bypass mode and Cache Bypass mode both use the same bypass ports, dma<n>_c2h_byp_in_st_csh_*.
Table 4. QDMA C2H-MM Channel 0 Descriptor Bypass Input Port Descriptions
Port Name I/O Description
dma<n>_c2h_byp_in_mm_<y>_raddr [63:0] I The read address for the DMA data.
dma<n>_c2h_byp_in_mm_<y>_wadr[63:0] I The write address for the DMA data.
dma<n>_c2h_byp_in_mm_<y>_no_dma I

C2H Bypass In No DMA

When sending in a descriptor through this interface with this signal asserted, this signal informs the QDMA to not send any PCIe requests for this descriptor. Because no PCIe request is sent out, no corresponding DMA data is read from C2H MM interface.

This is typically used in conjunction with dma<n>_c2h_byp_in_mm_<y>_sdi to cause Status Descriptor/Interrupt when the user logic is out of the actual descriptors and still wants to drive the dma<n>_c2h_byp_in_mm_<y>_sdi signal.

If dma<n>_c2h_byp_in_mm_<y>_mrkr_req and dma<n>_c2h_byp_in_mm_<y>_sdi are reset when sending in a no-DMA descriptor, the descriptor is treated as a NOP and is completely consumed inside the QDMA without any interface activity.

If dma<n>_c2h_byp_in_mm_<y>_no_dma is set, the QDMA ignores the address. The length field should be set to 0.

dma<n>_c2h_byp_in_mm_<y>_len[27:0] I The DMA data length
dma<n>_c2h_byp_in_mm_<y>_sdi I

C2H Bypass In Status Descriptor/Interrupt

If set, it is treated as an indication from the User to QDMA to send the status descriptor to host, and generate an interrupt to host when the QDMA has fetched the last byte of the data associated with this descriptor. The QDMA will honor the request to generate an interrupt only if interrupts have been enabled in the C2H ring context for this QID and armed by the driver.

dma<n>_c2h_byp_in_mm_<y>_mrkr_req I

C2H Bypass In Marker Request

Indication from the User that the QDMA must send a completion status to the User once the QDMA has completed the data transfer of this descriptor.

dma<n>_c2h_byp_in_mm_<y>_qid [10:0] I The QID associated with the C2H descriptor ring
dma<n>_c2h_byp_in_mm_<y>_error I This bit can be set to indicate an error for the queue. The descriptor will not be processed. Context will be updated to reflect and error in the queue.
dma<n>_c2h_byp_in_mm_<y>_func [11:0] I PCIe function ID
dma<n>_c2h_byp_in_mm_<y>_cidx [15:0] I The User must echo the CIDX from the descriptor that it received on the bypass-out interface.
dma<n>_c2h_byp_in_mm_<y>_port_id[2:0] I QDMA port ID
dma<n>_c2h_byp_in_mm_<y>_valid I Valid. High indicates descriptor is valid, one pulse for one descriptor.
dma<n>_c2h_byp_in_mm_<y>_ready O Ready to take in descriptor.
  1. variable <n> : represents different QDMAs (QDMA0 or QDMA1).
  2. variable <y> : represents different Channels, (Channel 0 or Channel 1 ).