QDMA Descriptor Bypass Output Interface - 3.3 English

Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2022-11-02
Version
3.3 English
Table 1. QDMA H2C Descriptor Bypass Output Interface Descriptions
Port Name I/O Description
dma0_h2c_byp_out_dsc[255:0] O The H2C descriptor fetched from the host.

For H2C AXI-MM, the QDMA uses all 256 bits, and the structure of the bits are the same as found in AXI Memory Mapped Writeback Status Structure for H2C and C2H.

For H2C AXI-ST, the QDMA uses [127:0] bits, and the structure of the bits are the same as found in H2C Stream Status Descriptor Writeback.

dma0_h2c_byp_out_st_mm O Indicates whether this is a streaming data descriptor or memory-mapped descriptor.

0: Streaming

1: Memory-mapped

dma0_h2c_byp_out_dsc_sz[1:0] O Descriptor size. This field indicates the size of the descriptor.

0: 8B

1: 16B

2: 32B

3: 64B - 64B descriptors will be transferred with two valid/ready cycles. The first cycle has the least significant 32 bytes. The second cycle has the most significant 32 bytes. CIDX and other queue information is valid only on the second beat of a 64B descriptor .

dma0_h2c_byp_out_qid[10:0] O The QID associated with the H2C descriptor ring.
dma0_h2c_byp_out_error O Indicates that an error was encountered in descriptor fetch or execution of a previous descriptor.
dma0_h2c_byp_out_func[7:0] O PCIe function ID
dma0_h2c_byp_out_cidx[15:0] O

H2C Bypass Out Consumer Index

The ring index of the descriptor fetched. The User must echo this field back to QDMA when submitting the descriptor on the bypass-in interface.

dma0_h2c_byp_out_port_id[2:0] O QDMA port ID
dma0_h2c_byp_out_mrkr_rsp O

Indicates completion status in response to h2c_byp_in_st_mrkr_req (Stream) or h2c_byp_in_mm_mrkr_req (MM).

dma0_h2c_byp_out_valid O Valid. High indicates descriptor is valid, one pulse for one descriptor.
dma0_h2c_byp_out_ready I Ready. When this interface is not used, Ready must be tied-off to 1.
Table 2. QDMA C2H Descriptor Bypass Output Port Descriptions
Port Name I/O Description
dma0_c2h_byp_out_dsc[255:0] O The C2H descriptor fetched from the host.

For C2H AXI-MM, the QDMA uses all 256 bits, and the structure of the bits is the same as found in AXI Memory Mapped Writeback Status Structure for H2C and C2H.

For C2H AXI-ST, the QDMA uses [63:0] bits, and the structure of the bits is the same as found in C2H Stream Descriptor (8B). The remaining bits are ignored.

dma0_c2h_byp_out_st_mm O Indicates whether this is a streaming data descriptor or memory-mapped descriptor.

0: streaming

1: memory-mapped

dma0_c2h_byp_out_dsc_sz[1:0] O Descriptor size. This field indicates the size of the descriptor.

0: 8B

1: 16B

2: 32B

3: 64B to 64B descriptors will be transferred with two valid/ready cycles. The first cycle has the least significant 32 bytes. The second cycle has the most significant 32 bytes. CIDX and other queue information is valid only on the second beat of a 64B descriptor.

dma0_c2h_byp_out_qid[10:0] O The QID associated with the H2C descriptor ring.
dma0_c2h_byp_out_error O Indicates that an error was encountered in descriptor fetch or execution of a previous descriptor.
dma0_c2h_byp_out_func[7:0] O PCIe function ID.
dma0_c2h_byp_out_cidx[15:0] O

C2H Bypass Out Consumer Index

The ring index of the descriptor fetched. The User must echo this field back to QDMA when submitting the descriptor on the bypass-in interface.

dma0_c2h_byp_out_port_id[2:0] O QDMA port ID
dma0_c2h_byp_out_mrkr_rsp O

Indicates completion status in response to s_axis_c2h_ctrl_marker (Stream) or c2h_byp_in_mm_mrkr_req (MM). For the completions status for dma0_s_axis_c2h_ctrl_marker (Stream), the details are given in the table below.

dma0_c2h_byp_out_valid O Valid. High indicates descriptor is valid, one pulse for one descriptor.
dma0_c2h_byp_out_ready I Ready. When this interface is not used, Ready must be tied-off to 1.
Table 3. QDMA C2H Descriptor Bypass out Marker Response Description
Field Name location Description
err[1:0] [1:0]

Error code reported by the C2H Engine.

0: No error

1: SW gave bad Completion CIDX update

2: Descriptor error received while processing the C2H packet

3: Completion dropped by the C2H Engine because Completion Ring was full

retry_marker_req [2]

The marker request could not be completed because an Interrupt could not be generated in spite of being enabled. This happens when an Interrupt is already outstanding on the queue when the marker request was received. The user logic must wait and retry the marker request again.

rsv [255:3] Reserved

It is common for dma0_h2c_byp_out_valid or dma0_c2h_byp_out_valid to be asserted with the CIDX value. This occurs when the descriptor bypass mode option is not set in the context programming selection. You must set the descriptor bypass mode during QDMA IP core customization in the Vivado® IDE to see descriptor bypass output ports. When the descriptor bypass option is selected in the Vivado IDE but the descriptor bypass bit is not set in context programming, you will see valid signals getting asserted with CIDX updates.