QDMA Global Ports - 3.3 English

Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2022-11-02
Version
3.3 English
Table 1. QDMA Global Port Descriptions
Port Name I/O Description
gt_refclk0_clk_p/gt_refclk0_clk_n I GT reference clock
PCIE0_GT_gtx_n/PCIE0_GT_gtx_p [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] O PCIe TX serial interface.
PCIE0_GT_grx_n/PCIE0_GT_grx_p [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] I PCIe RX serial interface.
dma<n>_intrfc_clk I User clock input. User needs to connected this pin to an independent clock source. All DMA interface output/input needs to driven/flopped from this clock source.
dma<n>_intrfc_resetn I Interface reset signals. User should release this signal (1'b1) after the clock dma<n>_intrfc_clk is stable, until then all the interface signals will be held in reset state.
cpm_pl_axi0_clk I This is AXI4-MM interface clock for channel 0. This clock will be exposed only when QDMA1 with AXI4-MM interface to PL is enabled and maximum frequency should be 250MHz.
cpm_pl_axi1_clk I This is AXI4-MM interface clock for channel 1. This clock will be exposed only when QDMA1 with AXI4-MM interface to PL is enabled and maximum frequency should be 250MHz.
dma<n>_axi_aresetn O User reset out. Reset out signal is synchronous to clock provided on dma<n>_interff_clk. This reset should drive all interface reset logic.

dma<n>_axi_aresetn is independent of PCIe reset.

When the DMA engine comes out of reset, dma<n>_axi_aresetn is de-asserted.

cpm_misc_irq O Reserved (future use)
cpm_cor_irq O Reserved (future use)
cpm_uncor_irq O Reserved (future use)
cpm_irq0 I Reserved (future use), tie this port to 1'b0
cpm_irq1 I Reserved (future use), tie this port to 1'b0