QDMA Management Ports - 3.3 English

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)
Document ID
PG347
Release Date
2023-05-16
Version
3.3 English
Table 1. QDMA Management Ports
Port Name I/O Description
dma0_mgmt_req_adr[31:0] I QDMA register address
dma0_mgmt_req_dat[31:0] I data value to be written.
dma0_mgmt_req_cmd[1:0] I 2'b00 : read

2'b01 : write

2'b10 : reserved

2'b11 : reserved
dma0_mgmt_req_fnc[12:0] I Function number
dma0_mgmt_req_msc[5:0] I Reserved. Assign all zeroes
dma0_mgmt_req_rdy O Ready
dma0_mgmt_req_vld I Valid, asserted for one clock cycle if rdy is asserted
dma0_mgmt_cpl_dat[31:0] O Data from QDMA IP
dma0_mgmt_cpl_rdy I Ready
dma0_mgmt_cpl_sts[1:0] O
  • bit[0] :
    • 1 Error
    • 0 good
  • bit[1] :
    • 1 write response
    • 0 read response
dma0_mgmt_cpl_vld O Valid asserted for one clock cycle, if rdy is asserted

QDMA Management port should be connected to mailbox ports as described below when SRIOV/Mailbox is enabled.

Note: Mailbox ports are always connected to Mailbox IP. If Mailbox IP is not used, leave the port unconnected (floating). See the following figure for connection reference.
Figure 1. CPM5 Mailbox Connection

The following connections are related to the above example design. To connect the Mailbox IP, follow these steps:

  1. Add PCIe QDMA Mailbox IP. To do so:
    1. Configure the IP for the number of PFs (should be same as number of PFs selected in QDMA configuration).
    2. Configure the IP for the number of VFs in each PF (should be same as number of VFs selected in QDMA configuration).
    Note: It is important to match number PFs and VFs to the numbers configured in the QMDA IP. If not, the design will not work.
  2. Re-configure the NoC IP to add one extra AXI Master port. To do so:
    1. Assign one more AXI clock.
    2. In the Outputs tab, assign M02_AXI to aclk2.
    3. In the Connectivity tab, select the M02_AXI PL option for both S00_AXI and SS01_AXI ps_pcie.
  3. Add AXI SmartConnect IP.
    1. Configure the IP to have one master, one slave, one clock, and one reset.

Follow the CPM5 Mailbox Connection figure above to make the necessary connections.

  1. Connect M02_AXI interface to Smartconnect1, from Smartconnect1, connect M00_AXI to Mailbox IP.
  2. Connect dma0_usr_irq from CIPS IP to the Mailbox IP output.
  3. Connect dma0_usr_flr from CIPS IP to the Mailbox IP output.
  4. Make usr_flr and usr_irq interface in the Mailbox IP as external pins.