QDMA Traffic Manager Credit Output Ports - 3.3 English

Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2022-11-02
Version
3.3 English
Table 1. QDMA TM Credit Output Port Descriptions
Port Name I/O Description
dma<n>_tm_dsc_sts_valid O Valid. Indicates valid data on the output bus. Valid data on the bus is held until tm_dsc_sts_rdy is asserted by the user.
dma<n>_tm_dsc_sts_rdy I Ready. Assertion indicates that the user logic is ready to accept the data on this bus. When this interface is not used, Ready must be tied-off to 1.
Note: When this interface is not used, Ready must be tied-off to 1.
dma<n>_tm_dsc_sts_byp O Shows the bypass bit in the SW descriptor context
dma<n>_tm_dsc_sts_dir O Indicates whether the status update is for a H2C or C2H descriptor ring.

0: H2C

1: C2H

dma<n>_tm_dsc_sts_mm O Indicates whether the status update is for a streaming or memory-mapped queue.

0: streaming

1: memory-mapped

dma<n>_tm_dsc_sts_qid [10:0] O The QID of the ring
dma<n>_tm_dsc_sts_avl [15:0] O If dma<n>_tm_dsc_sts_qinv is set, this is the number of credits available in the descriptor engine. If dma<n>_tm_dsc_sts_qinv is not set this is the number of new descriptors that have been posted to the ring since the last time this update was sent.
dma<n>_tm_dsc_sts_qinv O If set, it indicates that the queue has been invalidated. This is used by the user application to reconcile the credit accounting between the user application and QDMA.
dma<n>_tm_dsc_sts_qen O The current queue enable status.
dma<n>_tm_dsc_sts_irq_arm O If set, it indicates that the driver is ready to accept interrupts
dma<n>_tm_dsc_sts_error O Set to 1 if the PIDX update is rolled over the current CIDX of associated queue.
dma<n>_tm_dsc_sts_pidx[15:0] O PIDX of the Queue
dma<n>_tm_dsc_sts_port_id [2:0] O The port id associated with the queue from the queue context.