QDMA_TRQ_SEL_QUEUE_PF (0x6400) - 3.3 English

Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2022-11-02
Version
3.3 English
Table 1. QDMA_TRQ_SEL_QUEUE_PF (0x6400) Register Space
Register Address Description
QDMA_DMAP_SEL_INT_CIDX[2048] (0x6400) 0x6400-0xB3F0 Interrupt Ring Consumer Index (CIDX)
QDMA_DMAP_SEL_H2C_DSC_PIDX[2048] (0x6404) 0x6404-0xB3F4 H2C Descriptor Producer index (PIDX)
QDMA_DMAP_SEL_C2H_DSC_PIDX[2048] (0x6408) 0x6408-0xB3F8 C2H Descriptor Producer Index (PIDX)
QDMA_DMAP_SEL_CMPT_CIDX[2048] (0x640C) 0x640C-0xB3FC C2H Completion Consumer Index (CIDX)

There are 2048 Queues, each Queue will have more than four registers. All these registers can be dynamically updated at any time. This set of registers can be accessed based on the Queue number.

  • Queue number is absolute Qnumber [0 to 2047].
  • Interrupt CIDX address = 0x6400 + Qnumber*16
  • H2C PIDX address = 0x6404 + Qnumber*16
  • C2H PIDX address = 0x6408 + Qnumber*16
  • Write Back CIDX address = 0x640C + Qnumber*16

For Queue 0:

  • 0x6400 correspond to QDMA_DMAP_SEL_INT_CIDX
  • 0x6404 correspond to QDMA_DMAP_SEL_H2C_DSC_PIDX
  • 0x6408 correspond to QDMA_DMAP_SEL_C2H_DSC_PIDX
  • 0x640C correspond to QDMA_DMAP_SEL_WRB_CIDX

For Queue 1:

  • 0x6410 correspond to QDMA_DMAP_SEL_INT_CIDX
  • 0x6414 correspond to QDMA_DMAP_SEL_H2C_DSC_PIDX
  • 0x6418 correspond to QDMA_DMAP_SEL_C2H_DSC_PIDX
  • 0x641C correspond to QDMA_DMAP_SEL_WRB_CIDX

For Queue 2:

  • 0x6420 correspond to QDMA_DMAP_SEL_INT_CIDX
  • 0x6424 correspond to QDMA_DMAP_SEL_H2C_DSC_PIDX
  • 0x6428 correspond to QDMA_DMAP_SEL_C2H_DSC_PIDX
  • 0x642C correspond to QDMA_DMAP_SEL_WRB_CIDX