QDMA_TRQ_SEL_QUEUE_VF (0x3000) - 3.3 English

Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2022-11-02
Version
3.3 English

VF functions can access direct update registers per queue with offset (0x3000). The description for this register space is the same as QDMA_TRQ_SEL_QUEUE_PF (0x18000).

This set of registers can be accessed based on Queue number. Queue number is relative Qnumber for that VF .

  • Interrupt CIDX address = 0x3000 + Qnumber*16
  • H2C PIDX address = 0x3004 + Qnumber*16
  • C2H PIDX address = 0x3008 + Qnumber*16
  • Completion CIDX address = 0x300C + Qnumber*16

For Queue 0:

  • 0x3000 correspond to QDMA_DMAP_SEL_INT_CIDX
  • 0x3004 correspond to QDMA_DMAP_SEL_H2C_DSC_PIDX
  • 0x3008 correspond to QDMA_DMAP_SEL_C2H_DSC_PIDX
  • 0x300C correspond to QDMA_DMAP_SEL_WRB_CIDX

For Queue 1:

  • 0x3010 correspond to QDMA_DMAP_SEL_INT_CIDX
  • 0x3014 correspond to QDMA_DMAP_SEL_H2C_DSC_PIDX
  • 0x3018 correspond to QDMA_DMAP_SEL_C2H_DSC_PIDX
  • 0x301C correspond to QDMA_DMAP_SEL_WRB_CIDX