Root Port Enumeration - 3.3 English

Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

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3.3 English

Root Port PCIe enumeration is done through ECAM register space. Each PCIe device or function is allocated 4 KB address space which holds their PCIe Configuration Space register. The upper address field of the ECAM register space consists of the PCIe Bus Device Function number to select the target device. ECAM register space automatically routes and generates the appropriate PCIe Configuration Request TLP Type based on the target PCIe Bus Device Function number as well as the programmed Primary Bus Number, Secondary Bus Number, and Subordinate Bus Number field.

Enumeration process through the Root Port PCIe Bridge IP follows the standard PCIe Bus discovery as well as PCIe Configuration Space programming sequence, as defined by the PCIe Base Specification. Root Port PCIe Bridge lists all the PCIe capabilities enabled in the Root Port up to AER Capabilities register. The remaining PCIe capabilities registers in the Root Port Configuration Space are not visible in the standard PCIe Configuration Space link list, however they follow the standard PCIe Configuration Space layout. Bridge register in the Root Port use one of the PCIe User Extended Configuration Space region and is accessible when targeting the Root Port Bus Device Function number. All downstream devices (PCIe switches, Endpoints) attached to the Root Port show all PCIe capabilities registers without any limitation.

Root port configuration address offsets are not listed correctly. Next pointer address is not pointing to proper address below AER, this may result in wrong configuration values. Up to AER all listed values are correct. User can read Config extended space below AER with fixed targeted address, Target address values are listed below.

Table 1. PCIe Extended Capability for Root Port
PF0 Start Address
AER 0x100
2nd PCIE 0x1C0
VC 0x1F0
Loopback VSEC 0x330
DLL Feature Cap 0x3A0
16 GT Cap 0x3B0
Margining Cap 0x400
Coherent Data Path
Root Port Bridge IP has two choices for AXI4 data path. A coherent data path is routed through CCI-500 interconnects in the FPD by selecting the CPM-NOC-0 route in the CIPS CPM IP customization GUI. Alternatively, a non-coherent data path is routed directly to the NoC in the LPD by selecting the CPM-NOC-1 route in the CIPS CPM IP customization GUI.