- AXI4 and AXI-ST
- 4 PF and 250 VF's
- Each Function with two BAR's. One for QDMA configuration space and one for Bypass access to PL.
- Descriptor bypass and Internal Mode
Following is the procedure to generate a CPM5 QDMA simulation design:
- Open Vivado and select Open Example
Project option under Quick Start.
- From the Template options, select Versal CPM5 QDMA Simulation
Design under PCIe section. You can see the corresponding diagram
on the right-hand side description section. click
The Vivado wizard guides you through the board/part section. This example design is fixed to VPK120 board.
- Select the project name and directory and click Next to generate project.
- A new simulation project is displayed as shown below.
This project has cpm_qdma (EP design) and design_rp (root port model). And all the relevant files that are need for simulation.