The Register Space mentioned in this document can also be accessible through the AXI4 Memory Mapped Slave interface. All accesses to these registers will be based on the following AXI Base Addresses:
- For QDMA registers: Base Address =
- For Bridge registers: Base Address =
The offsets within each register space are the same as listed for the PCIe BAR accesses.
Please make sure that all transactions targeting these register spaces have
AWCACHE and ARCACHE set to
1’b0 (Non-Modifiable) and only
access it in 4 Bytes transactions.
- All transactions originating from Programmable Logic (PL) region, must have
an AXI Master that sets AxCACHE =
1’b0before it enters the AXI NOC.
- All transactions originating from the APU or RPU must be defined by a Memory
nGnREto ensure AxCACHE =
- All transactions originating from PPU has no additional requirement necessary.