The initial programming image is stored in and retrieved from a primary boot device. For Tandem PROM, this image contains both stages, and for Tandem PCIe, this image contains only stage 1. To calculate configuration performance, use the stage 1 image size as reported in the write_device_image log files.
When using Tandem PCIe, the stage 2 image is delivered over a secondary boot device. Depending on the delivery path and PCIe controller options, configuration performance can be up to 3.2 GB/s while configuring the programmable logic.
- CPM QDMA-MM to SBI: Gen3x16+ maximum expected bandwidth 3.2 GB/s
- CPM XDMA-MM to SBI: Gen3x16+ maximum expected bandwidth 3.2 GB/s
- CPM AXI-Bridge to SBI: Maximum expected Bandwidth 700 MB/s for 512-bit 64-byte transfers
- CPM MCAP VSEC to SBI: Maximum expected bandwidth 1 MB/s or slower
For more information regarding Versal Configuration and Boot, please consult Versal ACAP System Software Developers Guide (UG1304).