Traffic Manager Output Interface - 3.3 English

Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

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3.3 English
Note: The ports described below have a prefix of dma<n>_, which can be either dma0_ for QDMA Port 0 or dma1_ for QDMA Port 1.

The traffic manager interface provides details of a queue’s status to user logic, allowing user logic to manage descriptor fetching and execution. In normal operation, for an enabled queue, each time the irq_arm bit is asserted or PIDX of a queue is updated, the descriptor engine asserts dma<n>_tm_dsc_sts_valid. The dma<n>_tm_dsc_sts_avl signal indicates the number of new descriptors available since the last update. Through this mechanism, user logic can track the amount of work available for each queue. This can be used for prioritizing fetches through the descriptor engine’s fetch crediting mechanism or other user optimizations. On the valid cycle, the dma<n>_tm_dsc_sts_irq_arm indicates that the dma<n>_irq_arm bit was zero and was set. In bypass mode, this is essentially a credit for an interrupt for this queue. When a queue is invalidated by software or due to error, the dma<n>_tm_dsc_sts_qinv signal will be set. If this bit is observed, the descriptor engine will have halted new descriptor fetches for that queue. In this case, the contents on dma<n>_tm_dsc_sts_avl indicate the number of available fetch credits held by the descriptor engine. This information can be used to help user logic reconcile the number of credits given to the descriptor engine, and the number of descriptors it should expect to receive. Even after dma<n>_tm_dsc_sts_qin is asserted, valid descriptors already in the fetch pipeline will continue to be delivered to the DMA engine (internal mode) or delivered to the descriptor bypass output port (bypass mode).

Other fields of the dma<n>_tm_dsc_sts interface identify the queue id, DMA direction (H2C or C2H), internal or bypass mode, stream or memory mapped mode, queue enable status, queue error status, and port ID.

While the dma<n>_tm_dsc_sts interface is a valid/ready interface, it should not be back-pressured for optimal performance. Since multiple events trigger a dma<n>_tm_dsc_sts cycle, if internal buffering is filled, descriptor fetching will be halted to prevent generation of new events.