Using the High Speed Debug Port Over PCIe for Design Debug - 3.3 English

Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2022-11-02
Version
3.3 English

The high speed debug port (HSDP) allows the Vivado Design Suite to connect to the FPGA debug cores through non-JTAG interfaces. The standard Vivado Design Suite debug feature uses JTAG to connect to the hardware FPGA resources and performs debug through Vivado. This appendix focuses on using PCIe to perform debug over a PCIe link rather than the standard JTAG debug interface. This is referred to as HSDP-over-PCIe and allows for Vivado ILA waveform capture, VIO debug control, and interaction with other Xilinx debug cores using the PCIe link as the communication channel.

HSDP-over-PCIe should be used to perform FPGA debug remotely using the Vivado Design Suite debug feature when JTAG debug is not available. This is commonly used for data center applications where the FPGA is connected to a PCIe host system without any other connections to the hardware device.

Using debug over PCIe requires software, driver, and FPGA hardware design components. Because there is an FPGA hardware design component to HSDP-over-PCIe debug, you cannot perform debug until the FPGA is already loaded with a FPGA hardware design that implements HSDP-over-PCIe and PCIe link to the host PC is established. This is achieved by loading an HSDP-over-PCIe enabled design into the configuration flash on the board prior to inserting the card into the data center location. Because debug using HSDP-over-PCIe is dependent on the PCIe communication channel, this should not be used to debug PCIe link related issues.