HDMI 2.1 Transmitter Subsystem Product Guide (PG350) - 1.2 English

Document ID: PG350
Release Date: 2022-10-19
Version: 1.2 English

Introduction
Features
IP Facts
Overview
Navigating Content by Design Process
Subsystem Overview
Applications
Unsupported Features
Licensing and Ordering Information
License Type
License Checkers
Product Specification
Introduction
AXI4-Stream to Video Out Bridge
Video Timing Controller
HDMI 2.1 Transmitter
HDCP
HDCP Key Management
AUX Packets
InfoFrames
AVI InfoFrame
Audio InfoFrame
Vendor Specific InfoFrame (VSIF)
Dynamic Range and Mastering InfoFrame
General Control Packet
Enhanced Gaming and Media Features
Configuring Gaming Features
VTEM Packets
MVRR
Dynamic HDR
Dynamic HDR Configuration
Dynamic HDR Metadata
MTW Interrupt (XV_HDMITXSS1_HANDLER_DYNHDR_MWT)
Standards
Performance and Resource Utilization
Maximum Frequencies
Port Descriptions
AXI4-Stream Pinouts
Native Video Pinouts
Native Video (Vectored DE) Pinouts
CPU Interface
AXI4-Stream Video Interface
Native Video Interface
Native Video (Vectored DE) Interface
Audio Input Stream Interface
Audio Clock Regeneration Interface
Dynamic HDR Interface (Memory Mapped AXI4 Interface)
HDMI Link Output Interface
Data Display Channel Interface
HDCP 1.4 Key Input Interface (AXI4-Stream Slave Interface)
HDCP 2.3 Interrupt Outputs
HDCP 1.4 Interrupt Outputs
Miscellaneous Signals
Clocks and Resets
Designing with the Subsystem
General Design Guidelines
Audio Data Stream
AXI4-Stream Video Input Stream Interface
Native Video Input Interface
Native DE Video Input Interface
Interlaced Video
Clocking
Resets
Design Flow Steps
Customizing and Generating the Subsystem
Top Level Tab
Video Bridge Tab (AXI4-Stream Interface Only)
Example Design Tab (AXI4-Stream Interface Only)
User Parameters
Output Generation
Constraining the Subsystem
Required Constraints
Device, Package, and Speed Grade Selections
Clock Frequencies
Clock Management
Clock Placement
Banking
Transceiver Placement
I/O Standard and Placement
Simulation
Synthesis and Implementation
Example Design
Summary
Example Design Specifics
Running the Example Design
Overwrite Constraints: GT Lane Swap
Export the Generated Example Design
Build Software Application Using Vitis IDE
HDCP Key Utility
Formatting HDCP Keys for HDCP 1.x
Formatting HDCP Keys for HDCP 2.3
Running the Reference Design (MicroBlaze)
Running the Reference Design (A53 on Zynq UltraScale+ Devices)
Running the Reference Design (A72 on Versal Devices)
Verification, Compliance, and Interoperability
Interoperability
Hardware Testing
Video Resolutions
Tested Video Resolutions for TMDS: RGB 4:4:4 and YCbCr 4:4:4
Tested Video Resolutions for TMDS: YCbCr 4:2:2
Tested Video Resolutions for TMDS: YCbCr 4:2:0
Tested Video Resolutions for FRL Mode - YUV422
Tested Video Resolutions for FRL Mode - RGB, YUV444
Tested Video Resolutions for FRL Mode - YUV420
Upgrading
Port Changes for 2021.2
Port Changes for 2021.1
Port Changes for 2020.2
Debugging
Finding Help on Xilinx.com
Documentation
Answer Records
Master AR for HDMI 2.1 TX Subsystem
Technical Support
Debug Tools
Vivado Design Suite Debug Feature
Reference Boards
Hardware Debug
General Checks
Interface Debug
AXI4-Lite Interfaces
AXI4-Stream Interfaces
AXI4-Stream Audio Interface
Application Software Development
Device Drivers
Architecture
Usage
HDMI TX Subsystem Flow
Application Integration
HDCP TX Overview
HDCP TX Driver Integration
Integrate HDMI PHY Controller /HDMI GT Subsystem Driver for HDMI 2.1 TX Subsystem Use
Interrupts
Application Callback Functions
XV_HDMITXSS1_HANDLER_CONNECT
XV_HDMITXSS1_HANDLER_TOGGLE
XV_HDMITXSS1_HANDLER_STREAM_UP
XV_HDMITXSS1_HANDLER_STREAM_DOWN
XV_HDMITXSS1_HANDLER_VS
XV_HDMITXSS1_HANDLER_BRDGLOCK
XV_HDMITXSS1_HANDLER_BRDGUNLOCK
XV_HDMITXSS1_HANDLER_BRDGOVERFLOW (Debug Only)
XV_HDMITXSS1_HANDLER_BRDGUNDERFLOW (Debug Only)
XV_HDMITXSS1_HANDLER_FRL_CONFIG
XV_HDMITXSS1_HANDLER_FRL_FFE
XV_HDMITXSS1_HANDLER_FRL_START
XV_HDMITXSS1_HANDLER_FRL_STOP
XV_HDMITXSS1_HANDLER_TMDS_CONFIG
XV_HDMITXSS1_HANDLER_HDCP_AUTHENTICATE
XV_HDMITXSS1_HANDLER_ DYNHDR_MTW
HDMI PHY Controller /HDMI GT Subsystem Interrupt Handlers for HDMI 2.1 TX Subsystem
XHDMIPHY1_HDMI_HANDLER_TXINIT
XHDMIPHY1_HDMI_HANDLER_TXREADY
Example Application Overview
HDMI 2.1 TX Subsystem Interrupt Controlling Layer
Integration of HDMI 2.1 TX Interrupt Controlling Layer
Callbacks from HDMI 2.1 TX Interrupt Controlling Layer
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Revision History
Please Read: Important Legal Notices

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