The HDMI 2.1 TX Subsystem uses six clock domains. This section describes all the clocks required for the HDMI 2.1 TX Subsystem to function in your application.
- This is the processor domain. It has been tested to run at 100 MHz.
- A free-running clock input running at a fixed rate. The
frl_clkis used by the internal processing. It can come from the MMCM or the clock pin. See the following table for more information.
- A free-running input clock for the
AXI4-Stream video is supported. The
AXI4-Stream to Video Out bridge will convert
the input AXI4-Stream video into native
video clock stream running in the
video_clkdomain. See the following table for more information.
tx_video_clkfrom the HDMI PHY Controller/HDMI GT Subsystem is connected to the HDMI 2.1 TX Subsystem
video_clk, which supports both TMDS mode and FRL mode.
- In TMDS mode, the HDMI PHY Controller /HDMI GT Subsystem is configured to generate the actual TX video clock with respect to the actual selected video format.
- In FRL mode, the HDMI PHY Controller /HDMI GT Subsystem is configured to output a fixed rate clock. See the following table for more information.
- In FRL mode, the optional
video_cke_incan be enabled to control the actual video clock rate to be running at
- Free-running input clock running at the fixed rate. Used by the HDR Data Engine to process the HDR AUX packets and to read from the memory. See the following table for more information.
|Device Family||Speed Grade||GT PLL||frl_clk||video_clk||s_axis_video_aclk||m_hdr_axi_aclk|
|-1LV, -2LV||CPLL, QPLL||325 MHz||300 MHz||300 MHz||300 MHz|
|-1, -1L 6||CPLL||325 MHz||300 MHz||375 MHz||300 MHz|
|QPLL||380 MHz||375 MHz||375 MHz||300 MHz|
|-2, -2L, -3||CPLL, QPLL||450 MHz||400 MHz||375 MHz||300 MHz|
|Versal®||-1LP,-1LHP,-2LP||LCPLL,RPLL||325 MHz||300 MHz||300 MHz||300 MHz|
|-1MP,-2HP||380 MHz||375 MHz||375 MHz||300 MHz|
|-2MP,-3HP||450 MHz||400 MHz||375 MHz||300 MHz|
txoutclkfrom the HDMI PHY Controller /HDMI GT Subsystem is connected to the HDMI 2.1 TX Subsystem
link_clk, which supports both TMDS mode and FRL mode.
- In TMDS mode, the HDMI PHY Controller /HDMI GT Subsystem is configured to generate the actual TMDS clocks with respect to the actual selected video format.
- In FRL mode, the HDMI PHY Controller
Subsystem is configured to support 3, 6, 8, 10, and 12 Gb/s of
line rates based on a single MGT reference clock frequency (400 MHz).
link_clk= line rate/40 as the GT data width is set to 40 bits parallel bus.
|Line Rate (Gb/s)||link_clk (MHz)|
- This clock is used by the source audio streaming interface. This clock should be = 512 × audio sample rate.
The HDMI clock structure is illustrated in the following figure and table.
|TMDS||Source synchronous clock to HDMI interface (This is the actual clock on the HDMI cable).||
= 1/10 data rate(for data rates < 3.4 Gb/s)
Data rate = 2.97 Gb/s
TMDS clock = 2.97/10 = 297 MHz
= 1/40 data rate(for data rates > 3.4 Gb/s)
Data rate = 5.94 Gb/s
TMDS clock = 5.94/40 = 148.5 MHz
|Data||This is the actual data rate clock. This clock is not used in the system. It is only listed to illustrate the clock relations.||
= TMDS clock(for data rates < 3.4 Gb/s)
Data rate = 2.97 Gb/s
Data clock = TMDS clock * 1 = 297 MHz
= TMDS clock * 4
(for data rates > 3.4 Gb/s)
Data rate = 5.94 Gb/s
Data clock = TMDS clock * 4 = 594 MHz
TMDS clock = 148.5 MHz
|Link||Clock used for data interface between the HDMI PHY layer module and subsystem||
TMDS clock = 297 MHz
Data clock = 297 MHz
Link clock = 297 MHz/4 = 74.25 MHz
Data clock = 594 MHz
Link clock = 594 MHz/4 = 148.5 MHz
|Pixel||This is the internal pixel clock. This clock is not used in the system. It is only listed to illustrate the clock relations.||
For 8 bpc pixel clock = data clock
For 10 bpc pixel clock = data clock/1.25
For 12 bpc pixel clock = data clock/1.5
For 16 bpc pixel clock = data clock/2
Data clock = 297 MHz
For 8 bpc pixel clock = 297 MHz
For 10 bpc pixel clock = 297/1.25 = 237.6 MHz
For 12 bpc pixel clock = 297/1.5 = 198 MHz
For 16 bpc pixel clock = 297/1.5 = 148.5 MHz
|Video||Clock used for video interface||
clock = pixel clock/4
297 MHz/4 = 74.25 MHz for quad pixel wide interface
However, in FRL mode, the link is running at a fixed rate according to the line rate established between source and sink. Therefore, instead of calculating the actual clocks, it is more useful to find out the minimum required link rate to support certain video format.
For example, 8kp30, 8 BPC, 4 PPC are used to show how all the clocks are derived.
|Video Resolution||Horizontal Total||Horizontal Active||Vertical Total||Vertical Active||Frame Rate (Hz)|
The pixel clock represents the total number of pixels that need to be sent every second.
Therefore, for TMDS mode, the following calculation is used.
- Pixel clock = Htotal × Vtotal × Frame Rate = 9000 x 4400 x 30 = 1,188,000,000 = 1188 MHz
- Video clock = (Pixel clock)/PPC = 1188/4 = 297 MHz
- Data clock = (Pixel clock) x BPC/8 = 1188 x 8/8 = 1188 MHz
- Link clock = (Data clock)/PPC = 1188/4 = 297 MHz
In this example, the data clock is 1188 MHz, which is equivalent to 11.88 Gb/s. That exceeds the TMDS bandwidth. Therefore, FRL mode is used to carry this video.
The total bandwidth needed = (Pixel clock) x BPC (bits per component) x 3 (3 components for RGB video) x 18/16 (HDMI 2.1 uses 16/18 encoding scheme) = 1188 x 8 x 3 x 18 / 16 = 32.076 Gb/s
On the other hand, AXI4-Stream video only carries active video, for example, TPG only generates active video. Therefore, when calculating the "active pixel clock", only hactive and vactive are used.
- Active Pixel clock = HActive × Vactive × Frame Rate = 7680 x 4320 x 30 = 995,328,000 = 995.328 MHz
- s_axis_video_clk = (Active Pixel clock)/PPC = 995.328/4 = 248.832 MHz
The total bandwidth needed for active video = (Active Pixel clock) x BPC (bits per component) x 3 (3 components for RGB video) x 18 / 16 (HDMI 2.1 uses 16/18 encoding scheme) = 995.328 x 8 x 3 x 18 / 16 = 26.874 Gb/s
When the HDMI 2.1 TX Subsystem is running in FRL mode, one of the following modes can be selected.
|Line Rate||Max Total Bandwidth (Gb/s)|
|3 Gb/s @ 3 lanes||9|
|6 Gb/s @ 3 lanes||18|
|6 Gb/s @ 4 lanes||24|
|8 Gb/s @ 4 lanes||32|
|10 Gb/s @ 4 lanes||40|
|12 Gb/s @ 4 lanes||48|
The HDMI 2.1 specification (http://www.hdmi.org/manufacturer/specification.aspx) (section 6.5) also defines the concept of repeat count, which is to compress the blanking period when it does not carry any AUX metadata. Therefore, in this example, 8 Gb/s @ 4 lanes is sufficient to support 8kp30 video.