Clocks and Resets - 1.2 English

HDMI 2.1 Transmitter Subsystem Product Guide (PG350)

Document ID
PG350
Release Date
2022-04-27
Version
1.2 English

The following table provides an overview of the clocks and resets. See Clocking and Resets for more information.

Table 1. Clocks and Resets
Name I/O Width Description
s_axi_cpu_aclk I 1 AXI4-Lite CPU control interface clock.
s_axi_cpu_aresetn I 1 Reset, associated with s_axi_cpu_aclk (active-Low). The s_axi_cpu_aresetn signal resets the entire subsystem including the data path and AXI4-Lite registers.
s_axis_video_aclk I 1 AXI4-Stream video input clock.
s_axis_video_aresetn I 1 Reset, associated with s_axis_video_aclk (active-Low).Resets the AXI4-Stream data path for the video input.
s_axis_audio_aclk I 1 AXI4-Stream Audio input clock. (The audio streaming clock must be greater than or equal to 128 times the audio sample frequency)
s_axis_audio_aresetn I 1 Reset, associated with s_axis_audio_aclk (active-Low). Resets the AXI4-Stream data path for the audio input.
link_clk I 1 HDMI Link data output clock. This connects to the HDMI PHY Controller /HDMI GT Subsystemlink clock output.
video_clk I 1 Clock for the native video interface.
frl_clk I 1 Fixed FRL link clock.
m_hdr_axi_aclk I 1 Dynamic HDR memory mapped AXI4 interface clock.
m_hdr_axi_aresetn I 1 Dynamic HDR memory mapped AXI4 interface reset associated with m_hdr_axi_aclk clock (active-Low). Resets the Dynamic HDR data path.
  1. The reset should be asserted until the associated clock becomes stable.