Dynamic HDR Configuration - 1.2 English

HDMI 2.1 Transmitter Subsystem Product Guide (PG350)

Document ID
PG350
Release Date
2022-04-27
Version
1.2 English

Dynamic HDR uses the following configuration structure.

typedef struct
{
	u64 Address; /**< Dynamic HDR packet buffer address */
	u16 PktType; /**< 16 bit Packet Type */
	u16 PktLength; /**< 16 bit Packet Length */
	u8 GOF;	/**< GOF Value 0 or 1 only */
	u8 FAPA; /**<FAPA Location 0 or 1 only */
} XV_HdmiTxSs1_DynHdr_Config;

The following table provides details of the Dynamic HDR configuration structure variables and their relation.

Table 1. Dynamic HDR Configuration Structure
Info Frame Type PktType PktLength GOF FAPA
No Dynamic HDR 0 0 0 0/1
ST 2094-10 (Annex R) 1 1 Up to 65535 0/1 0/1
ETSI TS 103-433-1 2 2 Up to 65535 0/1 0/1
ITU-T H.265 CRI 3 3 Up to 65535 0/1 0/1
ST 2094-40 (Annex S) 4 4 Up to 65535 0/1 0/1
HDR10+ VSIF 5 28 0 N/A
  1. For more information, see https://ieeexplore.ieee.org/document/7513370.
  2. For more information, see https://www.etsi.org/deliver/etsi_ts/103400_103499/10343301/01.02.01_60/ts_10343301v010201p.pdf.
  3. For more information, see https://www.itu.int/rec/T-REC-H.265.
  4. For more information, see https://ieeexplore.ieee.org/document/9095450.

The following API functions are defined in the HDMI TX SS driver to facilitate the construction of the Dynamic HDR metadata info frames packets.

  • To configure the Dynamic HDR metadata buffer address, packet type, packet length, GOF, and FAPA values:
    void XV_HdmiTxSs1_DynHdr_Cfg(XV_HdmiTxSs1 *InstancePtr, XV_HdmiTxSs1_DynHdr_Config *CfgPtr)
  • To enable or disable the Dynamic HDR metadata info frame generation inside the hardware:
    void XV_HdmiTxSs1_DynHdr_Control(XV_HdmiTxSs1 *InstancePtr, u8 Flag)
  • To enable or disable the GOI Dynamic HDR metadata info frame generation inside the hardware:
    void XV_HdmiTxSs1_DynHdr_GOF_Control(XV_HdmiTxSs1 *InstancePtr, u8 Flag)