Example Design Tab (AXI4-Stream Interface Only) - 1.2 English

HDMI 2.1 Transmitter Subsystem Product Guide (PG350)

Document ID
PG350
Release Date
2022-04-27
Version
1.2 English

The Example Design tab is shown in the following figure.

Figure 1. Example Design Tab
Design Topology
Fixed to Pass-Through, to showcase the HDMI 2.1 system built with one HDMI 2.1 TX Subsystem and one HDMI 2.1 RX Subsystem, sharing the same HDMI PHY Controller /HDMI GT Subsystem.
Axilite Frequency
AXI4-Lite CPU clock fixed to 100 MHz in this example design.
HDMI PHY Controller Setting Section
Allows the configuration of the Transmitter PLL type and Receiver PLL Type to the HDMI PHY Controller /HDMI GT Subsystem prior generating the example design. NI-DRU is always enabled in this example design. See the HDMI PHY Controller LogiCORE IP Product Guide (PG333) / HDMI GT Controller LogiCORE IP Product Guide (PG334) for details about NI-DRU requirements.
Example Design Overview
A system block diagram to show the overview of the example design to be generated.