HDMI 2.1 Transmitter - 1.2 English

HDMI 2.1 Transmitter Subsystem Product Guide (PG350)

Document ID
PG350
Release Date
2022-04-27
Version
1.2 English

The HDMI 2.1 TX Subsystem converts video and audio streams into an HDMI stream based on the selected video format set by the processor through the CPU interface. The subsystem then transmits the HDMI stream to the PHY Layer (HDMI PHY Controller /HDMI GT Subsystem) which converts the data into electronic signals, then sent to an HDMI sink through an HDMI cable.

The HDMI 2.1 TX Subsystem supports both Transition Minimized Differential Signaling (TMDS) and Fixed Rate Link (FRL) protocol based on the capability of the connected HDMI sink. As shown in the following figure, the HDMI 2.1 Transmitter subcore contains two separate data paths. One is to encode the video stream into TMDS signal, the other is to packetize the video stream into FRL packets, adding FEC parity and encode it according to the 16b/18b coding mechanism introduced in the HDMI 2.1 specification. A data multiplexer is used to select TMDS or FRL sending to the PHY layer. The PHY layer is controlled by the HDMI PHY Controller /HDMI GT Subsystem, which is capable of supporting both TMDS and FRL (at rates up to 12 Gb/s).

Figure 1. HDMI 2.1 TX Subsystem Core Block Diagram
Note: An external level shifter (such as an ON Semiconductor NB7NQ621M) must be used for the TX Subsystem solution as the GT transmitter does not support TMDS level signaling.