Subsystem Facts Table | |
---|---|
Subsystem Specifics | |
Supported Device Family 1 |
Versal® ACAPs (GTYE5,GYTP) UltraScale+™ Families (GTHE4, GTYE4) 2 |
Supported User Interfaces | AXI4-Lite, AXI4-Stream |
Resources | |
Provided with Subsystem | |
Design Files | RTL |
Example Design | Vivado® IP integrator and associated software application example |
Test Bench | Not Provided |
Constraints File | XDC |
Simulation Model | Not Provided |
Supported S/W Driver 3 | Standalone |
Tested Design Flows 4 | |
Design Entry | Vivado® Design Suite |
Simulation | Not Provided |
Synthesis | Vivado Synthesis |
Support | |
Release Notes and Known Issues | Master Answer Record: 72277 |
All Vivado IP Change Logs | Master Vivado IP Change Logs: 72775 |
Xilinx Support web page | |
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