IP Facts - 1.2 English

HDMI 2.1 Transmitter Subsystem Product Guide (PG350)

Document ID
PG350
Release Date
2022-04-27
Version
1.2 English
Subsystem Facts Table
Subsystem Specifics
Supported Device Family 1

Versal® ACAPs (GTYE5,GYTP)

UltraScale+™ ™ Families (GTHE4, GTYE4) 2

Supported User Interfaces AXI4-Lite, AXI4-Stream
Resources

Performance and Resource Utilization web page

Provided with Subsystem
Design Files RTL
Example Design Vivado® IP integrator and associated software application example
Test Bench Not Provided
Constraints File XDC
Simulation Model Not Provided
Supported S/W Driver 3 Standalone
Tested Design Flows 4
Design Entry Vivado® Design Suite
Simulation Not Provided
Synthesis Vivado Synthesis
Support
Release Notes and Known Issues Master Answer Record: 72277
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Xilinx Support web page
  1. For a complete list of supported devices, see the Vivado IP catalog.
  2. For GTHE4, -1,-1M, -1L, -1LV, -2LV, and -2LVI parts, and for GTYE4, -1,-1M,-1L, and -1LV parts, the maximum supported FRL line rate is 8.0 Gb/s due to the limitation on CPLL and USRCLKs.
  3. Standalone driver details can be found in <Install Directory>/Vitis/<Release>/data/embeddedsw/doc/xilinx_drivers_api_toc.htm.

  4. For the supported versions of third-party tools, see the Xilinx Design Tools: Release Notes Guide.