Interrupts - 1.2 English

HDMI 2.1 Transmitter Subsystem Product Guide (PG350)

Document ID
PG350
Release Date
2022-04-27
Version
1.2 English

The following subcores in the HDMI 2.1 TX Subsystem can generate interrupts.

  • HDMI 2.1 Transmitter
  • HDCP 1.4 IP
  • HDCP 1.4 Timer
  • HDCP 2.3 IP

The HDMI 2.1 TX Subsystem IP has multiple interrupts sources:

  • Hardware I/O inputs (for example, HPD, SB_STATUS, bridge_locked, bridge FIFO overflow/underflow)
  • Video Stream inputs (for example, Video VSYNC)
  • Internal timer (for example, FRL timer)

All interrupts generated by the HDMI 2.1 TX Subsystem are listed here:

  1. HPD – Peripheral I/O to detect HDMI cable 5.0V signal
    1. Rising edge – Cable connected
    2. Falling edge – Cable disconnected
    3. Toggle – A pulse occurred on the HPD line with a pulse width between 50 and 99 ms.
  2. Link Ready – Every time the PHY Controller is reconfigured, the link_clk is regenerated. An HDMI TX sub-core register bit (link status bit) reflects the change of link_clk status. . When stable link_clk is detected, it is set to 1. When link_clk becomes unstable, it is set to 0. The Link Ready is an interrupt to detect the change of the link status bit.
    1. Rising edge – Link is up
    2. Falling edge – Link is down
  3. Vertical Sync – This is to reflect the change of HDMI TX sub-core vsync input signal in its video interface bus.
    1. Rising edge – Vertical Sync is detected
  4. Video Bridge Unlocked – The AXI4-Stream to Video Out Bridge video lock status.
    1. Rising edge – Bridge is locked with the incoming AXI4 Video Stream.
    2. Falling edge – Bridge is unlocked with the incoming AXI4 Video Stream.
  5. Video Bridge overflow – The AXI4-Stream to Video Out Bridge internal FIFO is overflow (For debugging purpose only)
  6. FRL Interrupts

    All FRL interrupts are triggered by the internal FRL timer interrupt. Then based on software state machines and status, interrupts are triggered accordingly.

    1. FRL Config interrupt
    2. FRL FFE interrupt
    3. FRL Start interrupt
    4. FRL Stop interrupt
    5. TMDS Config interrupt
  7. HDCP Interrupts (only available when HDCP is enabled in hardware)
    1. HDCP 1.4 Interrupt
    2. HDCP 1.4 Timer Interrupt
    3. HDCP 2.3 Interrupt
    4. HDCP 2.3 Timer Interrupt
  8. Dynamic HDR MTW Interrupt (only available when Dynamic HDR support is enabled in the hardware)
    1. Rising edge – Start of the MTW window.
Table 1. Mapping Between Interrupt Sources and Application Callback Functions
Interrupts Callback
HPD XV_HDMITXSS1_HANDLER_CONNECT
XV_HDMITXSS1_HANDLER_TOGGLE
Link Ready XV_HDMITXSS1_HANDLER_STREAM_UP
XV_HDMITXSS1_HANDLER_STREAM_DOWN
Note: Two callbacks are mapped to the same interrupt source.
Link Ready rising edge: Stream Up
Link Ready falling edge: Stream Down
Vertical Sync XV_HDMITXSS1_HANDLER_VS
Video Bridge Unlocked

XV_HDMITXSS1_HANDLER_BRDGLOCK

XV_HDMITXSS1_HANDLER_BRDGUNLOCK

Video Bridge Overflow XV_HDMITXSS1_HANDLER_BRDGOVERFLOW
Video Bridge Underflow XV_HDMITXSS1_HANDLER_BRDGUNDERFLOW
FRL Interrupt XV_HDMITXSS1_HANDLER_FRL_CONFIG
XV_HDMITXSS1_HANDLER_FRL_FFE
XV_HDMITXSS1_HANDLER_FRL_START
XV_HDMITXSS1_HANDLER_FRL_STOP
XV_HDMITXSS1_HANDLER_TMDS_CONFIG
HDCP 1.4 Interrupt  
HDCP 1.4 Timer Interrupt  
HDCP 2.3 Interrupt  
HDCP 2.3 Timer Interrupt  
 

XHdcp22Tx_TimerHandler

XV_HDMITXSS1_HANDLER_HDCP_AUTHENTICATE

XV_HDMITXSS1_HANDLER_HDCP_DOWNSTREAM_TOPOLOGY_AVAILABLE

XV_HDMITXSS1_HANDLER_HDCP_UNAUTHENTICATED

Note: This callback function is not directly mapped to any interrupt source. Instead it is executed when the HDCP authentication state machine has reached the authenticated state.
Dynamic HDR MTW Interrupt XV_HDMITXSS1_HANDLER_ DYNHDR_MWT