The following subcores in the HDMI 2.1 TX Subsystem can generate interrupts.
- HDMI 2.1 Transmitter
- HDCP 1.4 IP
- HDCP 1.4 Timer
- HDCP 2.3 IP
The HDMI 2.1 TX Subsystem IP has multiple interrupts sources:
- Hardware I/O inputs (for example, HPD, SB_STATUS, bridge_locked, bridge FIFO overflow/underflow)
- Video Stream inputs (for example, Video VSYNC)
- Internal timer (for example, FRL timer)
All interrupts generated by the HDMI 2.1 TX Subsystem are listed here:
HPD – Peripheral I/O to
detect HDMI cable 5.0V signal
- Rising edge – Cable connected
- Falling edge – Cable disconnected
- Toggle – A pulse occurred on the HPD line with a pulse width between 50 and 99 ms.
- Link Ready – Every time the PHY Controller is reconfigured, the
link_clkis regenerated. An HDMI TX sub-core register bit (link status bit) reflects the change of
link_clkstatus. . When stable
link_clkis detected, it is set to 1. When
link_clkbecomes unstable, it is set to 0. The Link Ready is an interrupt to detect the change of the link status bit.
- Rising edge – Link is up
- Falling edge – Link is down
- Vertical Sync – This is to
reflect the change of HDMI TX sub-core
vsyncinput signal in its video interface bus.
- Rising edge – Vertical Sync is detected
- Video Bridge Unlocked –
The AXI4-Stream to Video Out Bridge video lock status.
- Rising edge – Bridge is locked with the incoming AXI4 Video Stream.
- Falling edge – Bridge is unlocked with the incoming AXI4 Video Stream.
- Video Bridge overflow – The AXI4-Stream to Video Out Bridge internal FIFO is overflow (For debugging purpose only)
- FRL Interrupts
All FRL interrupts are triggered by the internal FRL timer interrupt. Then based on software state machines and status, interrupts are triggered accordingly.
- FRL Config interrupt
- FRL FFE interrupt
- FRL Start interrupt
- FRL Stop interrupt
- TMDS Config interrupt
- HDCP Interrupts (only available when HDCP
is enabled in hardware)
- HDCP 1.4 Interrupt
- HDCP 1.4 Timer Interrupt
- HDCP 2.3 Interrupt
- HDCP 2.3 Timer Interrupt
- Dynamic HDR MTW Interrupt (only available
when Dynamic HDR support is enabled in the hardware)
- Rising edge – Start of the MTW window.
Note: Two callbacks are mapped to the same interrupt source.
|Link Ready rising edge: Stream Up|
|Link Ready falling edge: Stream Down|
|Video Bridge Unlocked||
|Video Bridge Overflow||XV_HDMITXSS1_HANDLER_BRDGOVERFLOW|
|Video Bridge Underflow||XV_HDMITXSS1_HANDLER_BRDGUNDERFLOW|
|HDCP 1.4 Interrupt|
|HDCP 1.4 Timer Interrupt|
|HDCP 2.3 Interrupt|
|HDCP 2.3 Timer Interrupt|
Note: This callback function is not directly mapped to any interrupt source. Instead it is executed when the HDCP authentication state machine has reached the authenticated state.
|Dynamic HDR MTW Interrupt||XV_HDMITXSS1_HANDLER_ DYNHDR_MWT|