Native Video Interface - 1.2 English

HDMI 2.1 Transmitter Subsystem Product Guide (PG350)

Document ID
PG350
Release Date
2022-04-27
Version
1.2 English

The following table shows the signals for the native video interface. This interface is a standard video interface and runs at the video_clk clock rate. The data width is user-configurable in the Vivado IDE by setting Max Bits Per Component (BPC) and Number of Pixels Per Clock on Video Interface (PPC).

Table 1. Native Video Interface
Name I/O Width Description
video_clk 1 I 1 Video clock
NATIVE_VID_IN_active_video I 1 Active video
NATIVE_VID_IN_data I video_data_width 3 Data
NATIVE_VID_IN_hsync I 1 Horizontal sync
NATIVE_VID_IN_vsync I 1 Vertical sync
  1. video_clk is generated by the HDMI PHY Controller/HDMI GT Subsystem.
  2. When native video/native video (Vectored DE) interface is selected, s_axis_video_aclk and s_axis_video_aresetn are removed from the HDMI 2.1 TX Subsystem interface ports.
  3. video_data_width = 3*BPC*PPC.