XV_HDMITXSS1_HANDLER_STREAM_DOWN - 1.2 English

HDMI 2.1 Transmitter Subsystem Product Guide (PG350)

Document ID
PG350
Release Date
2022-04-27
Version
1.2 English

This interrupt is triggered every time the HDMI PHY Controller /HDMI GT Subsystem is reconfigured and the output clock is not stable for the HDMI 2.1 TX Subsystem to stream video.

The callback function might disable the TX TMDS clock by calling the HDMI PHY Controller /HDMI GT Subsystem API:

void XHdmiphy1_Clkout1OBufTdsEnable(XHdmiphy1 *InstancePtr,
                                    XHdmiphy1_DirectionType Dir,
                                    u8 Enable);