HDMI 2.1 Receiver Subsystem Product Guide (PG351) - 1.2 English

Document ID: PG351
Release Date: 2022-10-19
Version: 1.2 English

Introduction
Features
IP Facts
Overview
Navigating Content by Design Process
Subsystem Overview
Applications
Unsupported Features
Licensing and Ordering Information
License Type
License Checkers
Product Specification
Introduction
Video In to AXI4-Stream Bridge
HDMI 2.1 Receiver
HDCP
HDCP Key Management
AUX Packets
InfoFrames
AVI InfoFrame
Audio InfoFrame
Vendor Specific InfoFrame (VSIF)
Dynamic Range and Mastering InfoFrame
General Control Packet
Enhanced Gaming and Media Features
Dynamic HDR
Dynamic HDR Info Structure
Standards
Performance and Resource Utilization
Maximum Frequencies
Port Descriptions
AXI4-Stream Pinouts
Native Video Pinouts
Native Video (Vectored DE) Pinouts
CPU Interface
AXI4-Stream Video Interface
Native Video Interface
Native Video (Vectored DE) Interface
Audio Output Stream Interface
Audio Clock Regeneration Interface
Dynamic HDR Interface (Memory Mapped AXI4 Interface)
HDMI Link Input Interface
Data Display Channel Interface
HDCP 1.4 Key Input Interface (AXI4-Stream Slave Interface)
HDCP 2.3 Interrupt Outputs
HDCP 1.4 Interrupt Outputs
Miscellaneous Signals
Clocks and Resets
Designing with the Subsystem
General Design Guidelines
Audio Data Stream
AXI4-Stream Video Output Stream Interface
Native Video Output Interface
Native DE Video Output Interface
Clocking
Resets
Design Flow Steps
Customizing and Generating the Subsystem
Top Level Tab
Video Bridge Tab (AXI4-Stream Interface Only)
Example Design Tab (AXI4-Stream Interface Only)
User Parameters
Output Generation
Constraining the Subsystem
Required Constraints
Device, Package, and Speed Grade Selections
Clock Frequencies
Clock Management
Clock Placement
Banking
Transceiver Placement
I/O Standard and Placement
Simulation
Synthesis and Implementation
Example Design
Summary
Example Design Specifics
Running the Example Design
Overwrite Constraints: GT Lane Swap
Export the Generated Example Design
Build Software Application Using Vitis IDE
HDCP Key Utility
Formatting HDCP Keys for HDCP 1.x
Running the Reference Design (MicroBlaze)
Running the Reference Design (A53 on Zynq UltraScale+ Devices)
Running the Reference Design (A72 on Versal Devices)
Verification, Compliance, and Interoperability
Interoperability
Hardware Testing
Video Resolutions
Tested Video Resolutions for TMDS: RGB 4:4:4 and YCbCr 4:4:4
Tested Video Resolutions for TMDS: YCbCr 4:2:2
Tested Video Resolutions for TMDS: YCbCr 4:2:0
Tested Video Resolutions for FRL Mode - YCbCr422
Tested Video Resolutions for FRL Mode - RGB, YCbCr444
Tested Video Resolutions for FRL Mode - YCbCr420
Upgrading
Port Changes for 2021.2
Port Changes for 2021.1
Port Changes for 2020.2
Debugging
Finding Help on Xilinx.com
Documentation
Answer Records
Master AR for HDMI 2.1 RX Subsystem
Technical Support
Debug Tools
Vivado Design Suite Debug Feature
Reference Boards
Hardware Debug
General Checks
Interface Debug
AXI4-Lite Interfaces
AXI4-Stream Interfaces
AXI4-Stream Audio Interface
Application Software Development
Device Drivers
Architecture
Usage
HDMI RX Subsystem Flow
Application Integration
HDCP RX Overview
HDCP RX Driver Integration
Integrate HDMI PHY Controller /HDMI GT Subsystem Driver for HDMI 2.1 RX Subsystem Use
Interrupts
Application Callback Functions
XV_HDMIRXSS1_HANDLER_CONNECT
XV_HDMIRXSS1_HANDLER_AUX
XV_HDMIRXSS1_HANDLER_AUD
XV_HDMIRXSS1_HANDLER_LINKSTA
XV_HDMIRXSS1_HANDLER_STREAM_UP
XV_HDMIRXSS1_HANDLER_STREAM_DOWN
XV_HDMIRXSS1_HANDLER_STREAM_INIT
XV_HDMIRXSS1_HANDLER_FRL_CONFIG
XV_HDMIRXSS1_HANDLER_FRL_START
XV_HDMIRXSS1_HANDLER_TMDS_CONFIG
XV_HDMIRXSS1_HANDLER_HDCP_AUTHENTICATE
XV_HDMIRXSS1_HANDLER_VFP_CH
XV_HDMIRXSS1_HANDLER_VRR_RDY
XV_HDMIRXSS1_HANDLER_DYN_HDR
HDMI PHY Controller /HDMI GT Subsystem Interrupt Handlers for HDMI 2.1 RX Subsystem
XHDMIPHY1_HDMI_HANDLER_RXINIT
XHDMIPHY1_HDMI_HANDLER_RXREADY
Example Application Overview
HDMI 2.1 RX Subsystem Interrupt Controlling Layer
Integration of HDMI 2.1 RX Interrupt Controlling Layer
Callbacks from HDMI 2.1 RX Interrupt Controlling Layer
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Revision History
Please Read: Important Legal Notices

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