- Open the Vivado Design Suite and create a new project.
- In the pop-up window, press Next until you
get to the page to select the AMD part
or board for the project.
- Select the target board, then click (the ZCU102, ZCU106, VCK190, VCU118, and VEK280 are supported).
- A Vivado Project opens. In
Flow Navigator, PROJECT MANAGER, click IP
Catalog to open it. Then double-click HDMI 2.1 Receiver Subsystem in Video Connectivity.
- A Customize IP window opens. Configure the HDMI 2.1 RX Subsystem, then select OK.
- Refer to the Design Flow Steps chapter for a detailed description on Customizing and Generating the Subsystem.
- You can rename the IP component name, which is used as example design project name.
Important: To enable 8kp48, 8kp50, 8kp60/10kp60 YUV420, select Number of pixels per clock as 8. Otherwise, it is recommended that you select Number of pixels per clock as 4, which is sufficient to support up to 8k/10kp30.
Note: Due to a board design limitation, there is no available clock source on the VCU118 board for the NI-DRU reference clock. Therefore, if you are targeting the VCU118 board, the NI-DRU is disabled by default.
- The Generate Output Products dialog box opens. Select
Generate.Note: You can optionally select Skip if you only want to create an example design and leave the IP generation to a later stage.
- The IP component with provided name is added to Design Sources.
Right-click on it and select Open IP Example
Design.
- Choose the target Example project directory, then select OK.
- A new Vivado project
launches, in which an HDMI 2.1 Example
Design is generated with Block Design to show the system structure. Select
Run Synthesis, Implementation, and Generate
Bitstream to build the design. An overall system IP integrator
block diagram of the ZCU106-based example design is
shown:
