XV_HDMIRXSS1_HANDLER_TMDS_CONFIG - 1.2 English

HDMI 2.1 Receiver Subsystem v1.2 Product Guide (PG351)

Document ID
PG351
Release Date
2023-05-16
Version
1.2 English

This interrupt is triggered every time a the FRL training times out and the HDMI 2.1 RX goes to the TMDS or the HDMI 2.1 trains in the legacy state to support incoming TMDS, HDMI 2.0 stream.

The callback function must perform the following steps:

  1. Update the application to configure the clock for the RX source.
  2. Configure the PHY GT for HDMI 2.0 operation.
    u32 XHdmiphy1_Hdmi20Config(XHdmiphy1 *InstancePtr,
        u8 QuadId,
        XHdmiphy1_DirectionType Dir)

    where,

    • InstancePtr is a pointer to the XVphy core instance.
    • QuadId is the GT quad ID to operate on.
    • Dir is an indicator for TX or RX.
    Note: QuadId is not used and should be set to 0.
  3. Set the video clock for the RX Core's FRL peripheral to 0.
    XV_HdmiRx1_SetFrlVidClock(InstancePtr, Value)