Vivado® supports the Block Automation for Control, Interfaces and Processing System IP to aid in integrating it into the larger design. After adding the CIPS IP to the block diagram, the block automation banner pops up. Click Run Block Automation to open the block automation page.
- Memory Controller
- You can select x1/x2/x4 interleaved DDR4/LPDDR4 or a combination of DDR4+LPDDR4 controllers and a new/existing NoC to be connected to the CIPS IP core.
- PL clocks/PL resets
- You can select 0-4 PL clocks and 0-4 reset signals which are exposed to PL.
- Design Flows
- The two Design Flows are available and the selected flow is reflected in the CIPS IP.
When you click OK, a validate ready design is provided with input requirements.