High-Speed Debug Port (HSDP) - 3.2 English

Control Interfaces and Processing System v3.2 LogiCORE IP Product Guide (PG352)

Document ID
PG352
Release Date
2022-05-11
Version
3.2 English

High-Speed Debug Port is a protocol that provides debug and trace for the programmable logic (PL), processing system (PS) and the AI Engines. HSDP can use gigabit transceivers on the device to provide better performance than the JTAG interface.

As HSDP is a protocol, the transaction layer is handled by the Debug Packet Controller (DPC) and the link layer can be one of the four interfaces listed below:

  • JTAG
  • HSDP Aurora (hardened Aurora IP)
  • CPM PCIe Controller
  • PL Aurora (soft Aurora IP)
Warning: Be very careful when using the hardened HSDP Aurora as this can impose limitations on the GTY transceivers available to the rest of the design. For more information on the limitations, see XPIPE GTY Transceiver Channels table in Versal ACAP Technical Reference Manual (AM011). For more information on high-speed debug port see Integrated Debug chapter in Versal ACAP Technical Reference Manual (AM011).
Figure 1. High Speed Debug Port