PS-PL Trace - 3.2 English

Control Interfaces and Processing System v3.2 LogiCORE IP Product Guide (PG352)

Document ID
Release Date
3.2 English

You can generate Trace ATB signal to PL. AMBA® Trace Bus interrupt is generated from this option, which is connected to CoreSight™ module. CoreSight™ gets the debug information from different cores in PL and can feed the same to ILA/CIPS core.

Enabling PL to PS Advanced Trace Bus (ATB) ports will enable ATB ports on the CIPS IP that allows PL access to the advanced trace bus.

PL to PS System Trace Macrocell (STM) event port will enable the STM ports on the CIPS IP that allows PL access to the CoreSight™ System Trace Macrocell.

Off-Chip parallel trace allows to output trace data from the PS via MIO or EMIO to PL. The MIO bus is 16-bit wide at most, whereas the EMIO bus can be up to 32-bit wide. Enabling PL_Trace peripheral allows to then select MIO or EMIO from the IO panel view.

Note: When enabling Off-Chip parallel trace, the FPD DBG_TRACE_CLK frequency in the clock tab should also be set to the same frequency as trace_ref_clk signal from PL to PS.

For trace via EMIO, a PL IP can be used to connect to the PS-PL trace interface and output to the PL XIOs the trace data according to the Arm® Trace standard. The PL XIOs are typically connected to a Mictor connector where a trace probe can collect the trace data for analysis in a debugging IDE.

Figure 1. PS-PL Trace Configuration