The ATG provides three methods for traffic pattern programming:
- Instruction block RAM (mem_v1_2_tg_instr_bram.sv)
- Used for regression with predefined traffic instructions
- Defines default traffic pattern
- Override default traffic pattern (re-compilation required)
- Direct instruction through VIO input
- Used for quick Debug with SINGLE traffic instruction
- Reprogram through VIO without re-compilation
- Program instruction table
- Used for Debug with MULTIPLE traffic instructions
- Reprogram through VIO without re-compilation
This document assumes debug using “Direct Instruction through VIO.” The same concepts
extend to both “Instruction Block RAM” and “Program Instruction Table.” “Direct
Instruction through VIO” is enabled using vio_tg_direct_instr_en.
After vio_tg_direct_instr_en is set to 1, all of the traffic
instruction fields can be driven by the targeted traffic instruction.
The following are VIO signals:
-
vio_tg_instr_addr_mode -
vio_tg_instr_data_mode -
vio_tg_instr_data_mode -
vio_tg_instr_rw_submode -
vio_tg_instr_victim_mode -
vio_tg_instr_victim_aggr_delay -
vio_tg_instr_num_of_iter -
vio_tg_instr_m_nops_btw_n_burst_m -
vio_tg_instr_m_nops_btw_n_burst_n -
vio_tg_instr_nxt_instr