AXI Addressing - 1.0 English

The AXI address from the AXI master is a TRUE byte address. The AXI shim converts the address from the AXI master to the memory based on AXI SIZE and memory data width. The LSBs of the AXI byte address are masked to 0, depending on the data width of the memory array. If the memory array is 64 bits (8 bytes) wide, AXI address[2:0] are ignored and treated as 0. If the memory array is 16 bits (2 bytes) wide, AXI address[0] is ignored and treated as 0. DDR4 DRAM is accessed in blocks of DRAM bursts and this memory controller always uses a fixed burst length of 8. The UI Data Width is always eight times the PAYLOAD_WIDTH.