AXI4-Lite Slave Control/Status Register Interface Parameters - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)
Document ID
PG353
Release Date
2023-10-18
Version
1.0 English

The following table lists the AXI4-Lite slave interface parameters.

Table 1. AXI4-Lite Slave Control/Status Register Parameters
Parameter Name Default Value Allowable Values Description
C_S_AXI_CTRL_ADDR_WIDTH 32 32 This is the width of the AXI4-Lite address buses.
C_S_AXI_CTRL_DATA_WIDTH 32 32 This is the width of the AXI4-Lite data buses.
C_ECC_ONOFF_RESET_VALUE 1 0, 1 Controls ECC ON/OFF value at startup/reset.
C_ECC_TEST OFF ON, OFF When ON, you can inject faults on the first burst of data/ECC.