AXI4-Lite Slave Control/Status Register Interface Signals - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)
Document ID
PG353
Release Date
2023-10-18
Version
1.0 English

The following table lists the AXI4-Lite slave interface specific signals. Clock/reset to the interface is provided from the Memory Controller.

Table 1. List of New I/O Signals
Name Width I/O Active State Description
s_axi_ctrl_awaddr C_S_AXI_CTRL_ADDR_WIDTH I Write address
s_axi_ctrl_awvalid 1 I High Write address valid. This signal indicates that valid write address and control information are available.
s_axi_ctrl_awready 1 O High Write address ready. This signal indicates that the slave is ready to accept an address and associated control signals.
s_axi_ctrl_wdata C_S_AXI_CTRL_DATA_WIDTH I Write data
s_axi_ctrl_wvalid 1 I High Write valid. This signal indicates that write data and strobe are available.
s_axi_ctrl_wready 1 O High Write ready
s_axi_ctrl_bvalid 1 O High Write response valid
s_axi_ctrl_bresp2 2 O Write response
s_axi_ctrl_bready 1 I High Response ready
s_axi_ctrl_araddr C_S_AXI_CTRL_ADDR_WIDTH I Read address
s_axi_ctrl_arvalid 1 I High Read address valid
s_axi_ctrl_arready 1 O High Read address
s_axi_ctrl_rdata C_S_AXI_CTRL_DATA_WIDTH O Read data
s_axi_ctrl_rresp 2 O Read response
s_axi_ctrl_rvalid 1 O Read valid
s_axi_ctrl_rready 1 I Read ready
interrupt 1 O High IP Global Interrupt signal