The AXI4 slave interface block maps AXI4 transactions to the UI to provide an industry-standard bus protocol interface to the Memory Controller. The AXI4 slave interface is optional in designs provided through the DDR4 SDRAM tool. The RTL is consistent between both tools. For details on the AXI4 signaling protocol, see the AMBA AXI4-Stream Protocol Specification (ARM IHI 0051A).
The overall design is composed of separate blocks to handle each AXI channel, which allows for independent read and write transactions. Read and write commands to the UI rely on a simple round-robin arbiter to handle simultaneous requests.
The address read/address write modules are responsible for chopping the AXI4 incr/wrap requests into smaller memory size burst lengths of either four or eight, and also conveying the smaller burst lengths to the read/write data modules so they can interact with the user interface. Fixed burst type is not supported.
If ECC is enabled, all write commands with any of the mask bits enabled are issued as read-modify-write operation. Also if ECC is enabled, all write commands with none of the mask bits enabled are issued as write operation.