The following figure shows the write full transfer timing diagram.
| Aligned (ADDR A) | AXI data width = 32-bit | AWID = 0 | AWADDR = 'h0 | AWSIZE = 2 | AWLEN = 3 | AWBURST = INCR |
| Unaligned (ADDR B) | AXI data width = 32-bit | AWID = 1 | AWADDR = 'h3 | AWSIZE = 2 | AWLEN = 3 | AWBURST = INCR |
Figure 1. Write Full Transfer
The following figure shows the read full transfer timing diagram.
| Aligned (ADDR A) | AXI data width = 32-bit | ARID = 0 | ARADDR = 'h0 | ARSIZE = 2 | ARLEN = 3 | ARBURST = INCR |
| Unaligned (ADDR B) | AXI data width = 32-bit | ARID = 1 | ARADDR = 'h3 | ARSIZE = 2 | ARLEN = 3 | ARBURST = INCR |
Figure 2. Read Full Transfer
The following figure shows the write narrow transfer timing diagram.
| Aligned (ADDR A) | AXI data width = 32-bit | AWID = 0 | AWADDR = 'h0 | AWSIZE = 1 | AWLEN = 3 | AWBURST = INCR |
| Unaligned (ADDR B) | AXI data width = 32-bit | AWID = 1 | AWADDR = 'h3 | AWSIZE = 1 | AWLEN = 3 | AWBURST = INCR |
Figure 3. Write Narrow Transfer
The following figure shows the read narrow transfer timing diagram.
| Aligned (ADDR A) | AXI data width = 32-bit | ARID = 0 | ARADDR = 'h0 | ARSIZE = 1 | ARLEN = 3 | ARBURST = INCR |
| Unaligned (ADDR B) | AXI data width = 32-bit | ARID = 1 | ARADDR = 'h3 | ARSIZE = 1 | ARLEN = 3 | ARBURST = INCR |
Figure 4. Read Narrow Transfer
