Additive Latency - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)

Document ID
PG353
Release Date
2023-10-18
Version
1.0 English

The PHY supports DRAM additive latency. The only effect on the PHY interface due to enabling Additive Latency (AL) in the MRS parameters is in the timing of the wrDataEn signal after mcWrCAS assertion. The PHY takes the AL setting into account when scheduling wrDataEn. You can also find the rdDataEn asserts much later after mcRdCAS because the DRAM returns data much later. The AL setting also has an impact on whether or not the EXTRA_CMD_DELAY parameter needs to be set to a non-zero value.