The Memory Controller generates even command/address parity with a one DRAM clock delay after the chip select asserts Low. This signal is only used in DDR4 RDIMM configurations where parity is required by the DIMM RCD component.
Address parity is supported only for DDR4 RDIMM and LRDIMM configurations, which includes 3DS RDIMMs
and LRDIMMs. The Memory Controller does not monitor the Alert_n parity
error status output from the RDIMM/LRDIMM and it might return corrupted data to the User
Interface after a parity error.
The Alert_n signal is provided to the user through the user
interface.