CAL_ERROR Decode for DQS Preamble Detection Calibration - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)

Document ID
PG353
Release Date
2023-10-18
Version
1.0 English

The status of DQS Gate can also be determined by decoding the CAL_ERROR result according to table below. Execute the Tcl commands noted in the Manually Analyzing the XSDB Output section to generate the XSDB output containing the signal results.

Table 1. CAL_ERROR Decode for DQS Preamble Detection Calibration
Error Code Description Recommended Debug Step
6 DQS gating timeout waiting for XPHY gate training done. Check power and pinout on the PCB/Design. This is the error found when the DRAM does not respond to the Read command. Probe if the read DQS is generated when a read command is sent out.
7 DQS gating reached maximum read latency limit. Check DQS and CK trace lengths. Ensure the maximum trace length is not violated. For debug purposes, try a lower frequency where more search range is available and check if the stage is successful.
8 DQS gating reached maximum read latency limit. Check DQS and CK trace lengths for all the ranks. Ensure the maximum trace length is not violated. For debug purposes, try a lower frequency.