CAL_ERROR Decode for Read Per-Bit DQ Deskew Calibration - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)

Document ID
PG353
Release Date
2023-10-18
Version
1.0 English

The status of Read Per-Bit DQ Deskew can also be determined by decoding the CAL_ERROR result according to the table below. Execute the Tcl commands noted in the Manually Analyzing the XSDB Output section to generate the XSDB output containing the signal results.

Table 1. CAL_ERROR Decode for Read Per-Bit DQ Deskew Calibration
Error Code Description Recommended Debug Step
12 No valid data found for a given bit in the nibble by incrementing PQTR/NQTR IDELAY together using step size of 1 tap. Check the dbg_rd_data, dbg_rd_data_cmp, and dbg_expected_data signals in the ILA. Check the pinout and look for any STUCK-AT-BITs, check vrp resistor, VREF resistor. Check BRAM_BISC_PQTR, BRAM_BISC_NQTR for starting offset between rising/falling clocks.
13 No valid data found for a given bit in the nibble by incrementing DQ IDELAY using step size of 1 tap. Check the dbg_rd_data, dbg_rd_data_cmp, and dbg_expected_data signals in the ILA. Check the pinout and look for any STUCK-AT-BITs, check vrp resistor, VREF resistor. Check BRAM_BISC_PQTR, BRAM_BISC_NQTR for starting offset between rising/falling clocks.
14 Noise region not found for a given bit in the nibble by incrementing DQ IDELAY using step size of 10 taps. Check for a mapping issue. This usually implies a delay is not moving when it should. Check the connections going to the XPHY and ensure the correct RIU is selected based on the byte being adjusted.
15 Noise region not found for a given bit in the nibble by incrementing DQ IDELAY using step size of 1 tap. Check for a mapping issue. This usually implies a delay is not moving when it should. Check the connections going to the XPHY and ensure the correct RIU is selected based on the byte being adjusted.