CAS Command Timing Limitations - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)

Document ID
PG353
Release Date
2023-10-18
Version
1.0 English

The PHY only supports CAS commands on even command slots, that is, 0 and 2. This limitation is due to the complexity of the PHY logic driven by the PHY control inputs, like the mcWrCAS and mcRdCAS signals, not the actual DRAM command signals like mc_ACT_n[7:0], which just pass through the PHY after calDone asserts. The PHY logic is complex because it generates XPHY control signals based on the DRAM CWL and CL values with DRAM clock resolution, not just system clock resolution.

Supporting two different command slots for CAS commands adds a significant amount of logic on the XPHY control paths. There are very few pipeline stages available to break up the logic due to protocol requirements of the XPHY. CAS command support on all four slots would further increase the complexity and degrade timing.