This register stores the lower 32 bits of the decoded DRAM address (Bits[31:0]) of the first occurrence of an access with a correctable error. The address format is defined in the Error Address section. When the CE_STATUS bit in the ECC Status register is cleared, this register is re-enabled to store the address of the next correctable error. Storing of the failing address is enabled after reset.
Bits | Name | Core Access | Reset Value | Description |
---|---|---|---|---|
31:0 | CE_FFA[31:0] | R | 0 | Address (Bits[31:0]) of the first occurrence of a correctable error. |