This register stores the upper 32 bits of the decoded DRAM address
(Bits[55:32]) of the first occurrence of an access with a correctable error. The
address format is defined in the Error Address section. In addition, the upper byte
of this register stores the ecc_single
signal. When the CE_STATUS
bit in the ECC Status register is cleared, this register is re-enabled to store the
address of the next correctable error. Storing of the failing address is enabled
after reset.
Bits | Name | Core Access | Reset Value | Description |
---|---|---|---|---|
31:24 | CE_FFA[63:56] | R | 0 | ecc_single[7:0]. Indicates which bursts of the BL8 transaction associated with the logged address had a correctable error. Bit[24] corresponds to the first burst of the BL8 transfer. |
23:0 | CE_FFA[55:32] | R | 0 | Address (Bits[55:32]) of the first occurrence of a correctable error. |