CE_FFE - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)

Document ID

PG353

Release Date

2023-10-18

Version

1.0 English

This register stores the ECC bits of the first occurrence of an access with a correctable error. When the CE_STATUS bit in the ECC Status register is cleared, this register is re-enabled to store the ECC of the next correctable error. Storing of the failing ECC is enabled after reset.

The table describes the register bit usage when DQ_WIDTH = 72.

Table 1. Correctable Error First Failing ECC Register for 72-Bit External Memory Width
Bits	Name	Core Access	Reset Value	Description
7:0	CE_FFE	R	0	ECC (Bits[7:0]) of the first occurrence of a correctable error.

The table describes the register bit usage when DQ_WIDTH = 144.

Table 2. Correctable Error First Failing ECC Register for 144-Bit External Memory Width
Bits	Name	Core Access	Reset Value	Description
15:0	CE_FFE	R	0	ECC (Bits[15:0]) of the first occurrence of a correctable error.